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product structure silicon monolithic integrated circuit this product is not designed prot ection against radioactive rays 1/36 tsz02201-0r2r0g100290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 14 ? 001 www.rohm.com datashee t serial eeprom series standard eeprom i 2 c bus eeprom (2-wire) br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) general description br24lxxx - w series is a serial eeprom of i 2 c bus interface method features ? completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock (scl) and serial data (sda) ? other devices than eeprom can be connected to the same port, saving microcontroller port ? 1.8v to 5.5v *1 single power source action most suitable for battery use ? page write mode useful for initial value write at factory shipment ? highly reliable connection by au pad and au wire ? auto erase and auto end function at data write ? low current consumption ? at write operation (5v) : 1.2ma (typ.) *2 ? at read operation (5v) : 0.2ma (typ.) ? at standby operation (5v) : 0.1 a (typ.) ? write mistake prevention function ? write (write protect) function added ? write mistake prevention function at low voltage ? data rewrite up to 1,000,000 times ? data kept for 40 years ? noise filter built in scl / sda terminal ? shipment data all address ffh packages w(typ.) x d(typ.) x h(max.) *1 br24l02-w, br24l16-w, br24l32-w : 1.7v to 5.5v *2 br24l32-w, br24l64-w : 1.5ma page write number of pages 8byte 16byte 32byte product number br24l01a-w br24l02-w br24l04-w br24l08-w br24l16-w br24l32-w br24l64-w br24lxxx-w series capacity bit format type power source voltage sop8 sop-j8 ssop-b8 tssop-b8 msop8 tssop-b8j vson008 x2030 1kbit 1288 br24l01a-w 1.8v to 5.5v 2kbit 2568 br24l02-w 1.7v to 5.5v 4kbit 5128 br24l04-w 1.8v to 5.5v 8kbit 1k8 br24l08-w 1.8v to 5.5v 16kbit 2k8 br24l16-w 1.7v to 5.5v 32kbit 4k8 br24l32-w 1.7v to 5.5v 64kbit 8k8 br24l64-w 1.8v to 5.5v v son008x2030 2.00mm x 3.00mm x 0.60mm tssop-b8 3.00mm x 6.40mm x 1.20mm sop8 5.00mm x 6.20mm x 1.71mm sop- j8 4.90mm x 6.00mm x 1.65mm tssop-b8j 3.00mm x 4.90mm x 1.10mm msop8 2.90mm x 4.00mm x 0.90mm ssop-b8 3.00mm x 6.40mm x 1.35mm downloaded from: http:///
datasheet 2/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com absolute maximum ratings (ta=25 ) parameter symbol ratings unit remarks supply voltage v cc -0.3 to +6.5 v 450 (sop8) when using at ta=25 or higher 4.5mw to be reduced per 1 . 450 (sop-j8) when using at ta=25 or higher 4.5mw to be reduced per 1 . 300 (ssop-b8) when using at ta=25 or higher 3.0mw to be reduced per 1 . 330 (tssop-b8) when using at ta=25 or higher 3.3mw to be reduced per 1 . 310 (tssop-b8j) when using at ta=25 or higher 3.1mw to be reduced per 1 . 310 (msop8) when using at ta=25 or higher 3.1mw to be reduced per 1 . power dissipation pd 300 (vson008x2030) mw when using at ta=25 or higher 3.0mw to be reduced per 1 . storage temperature tstg 65 to +125 operating temperature topr 40 to +85 terminal voltage \ -0.3 to vcc+1.0 v memory cell characteristics (ta=25 , vcc=1.8v to 5.5v) *1 limits parameter min. typ. max. unit number of data rewrite times *2 1,000,000 - - times data hold years *2 40 - - years shipment data all address ffh *1 br24l02/16/32-w : 1.7v to 5.5v *2 not 100% tested recommended operating ratings parameter symbol ratings unit power source voltage vcc 1.8 to 5.5 *1 input voltage v in 0 to vcc v *1 br24l02/16/32-w : 1.7v to 5.5v electrical characteristics (unless otherwise specified, ta=-40 to +85 , v cc =1.8v to 5.5v) *1 limits parameter symbol min. typ. max. unit conditions high input voltage 1 v ih1 0.7vcc - vcc +1.0 *2 v 2.5 vcc 5.5v low input voltage 1 v il1 -0.3 *2 - 0.3 vcc v 2.5 vcc 5.5v high input voltage 2 v ih2 0.8vcc - vcc +1.0 *2 v 1.8 vcc 2.5v low input voltage 2 v il2 -0.3 *2 - 0.2 vcc v 1.8 vcc 2.5v high input voltage 3 *3 v ih3 0.8vcc - vcc +1.0 v 1.7 vcc 1.8v high input voltage 3 *4 v ih3 0.9vcc - vcc +1.0 v 1.7 vcc 1.8v low input voltage 3 *2 v il3 -0.3 - 0.1 vcc v 1.7 vcc 1.8v low output voltage 1 v ol1 - - 0.4 v i ol =3.0ma, 2.5v vcc 5.5v, (sda) low output voltage 2 v ol2 - - 0.2 v i ol =0.7ma, 1.7v vcc 2.5v, (sda) input leak current i li -1 - 1 av in =0v to vcc output leak current i lo -1 - 1 av out =0v to vcc, (sda) 2.0 *5 i cc1 - - 3.0 *6 ma vcc=5.5v,fscl=400khz, twr=5ms, byte write, page write current consumption at action i cc2 - - 0.5 ma vcc=5.5v,fscl=400khz random read, current read,sequential read standby current i sb - - 2.0 a vcc=5.5v, sda ? scl=vcc a0, a1, a2=gnd, wp=gnd *1 br24l02/16/32-w : 1.7v to 5.5v, *2 br24l16/32-w, *3 br24l02/16-w, *4 br24l32-w *5 br24l01a/02/04/08/16-w, *6 br24l32/64-w downloaded from: http:///
datasheet 3/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com action timing characteristics (unless otherwise specified, ta= - 40 to +85 , v cc =1.8v to 5.5v) *1 fast-mode 2.5v vcc 5.5v standard-mode 1.8v vcc 5.5v parameter symbol min. typ. max. min. typ. max. unit scl frequency fscl - - 400 - - 100 khz data clock high time thigh 0.6 - - 4.0 - - s data clock low time tlow 1.2 - - 4.7 - - s sda, scl rise time *2 tr - - 0.3 - - 1.0 s sda, scl fall time *2 tf - - 0.3 - - 0.3 s start condition hold time thd:sta 0.6 - - 4.0 - - s start condition setup time tsu:sta 0.6 - - 4.7 - - s input data hold time thd:dat 0 - - 0 - - ns input data setup time tsu:dat 100 - - 250 - - ns output data delay time tpd 0.1 - 0.9 0.2 - 3.5 s output data hold time tdh 0.1 - - 0.2 - - s stop condition setup time tsu:sto 0.6 - - 4.7 - - s bus release time before transfer start tbuf 1.2 - - 4.7 - - s internal write cycle time twr - - 5 - - 5 ms noise removal valid period (sda, scl terminal) ti - - 0.1 - - 0.1 s wp hold time thd:wp 0 - - 0 - - ns wp setup time tsu:wp 0.1 - - 0.1 - - s wp valid time thigh:wp 1.0 - -- 1.0 - - s *1 br24l02/16/32-w : 1.7v to 5.5v *2 not 100% tested fast-mode and standard-mode fast-mode and standard-mode are of same actions, and mode is changed. they are distinguished by action speeds. 100khz action is called standard-mode, and 400khz action is called fast-mode. this action frequency is the maximum action frequency, so 100khz clock may be used in fast-mode. when power source voltage goes down, action at high speed is not carried out, therefore, at vcc=2.5v to 5.5v , 400khz, namely, action is made in fastmode. (action is made also in standard-mode) vcc=1.8v to 2. 5v is only action in 100khz standard-mode. downloaded from: http:///
datasheet 4/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com sync data input / output timing sda tsu:sta tsu:sto thd:sta start bit stop bit scl input read at the rise edge of scl data output in sync with the fall of scl figure 1-(a) sync data input / output timing figure 1-(b) start-stop bit timing sda write data ( n-th address ) stop condition start condition scl wr ack d0 figure 1-(c) write cycle timing figure 1-(d) wp timing at write execution thigh:wp wp sda d1 d0 ack ack data(1) data(n) twr scl at write execution, in the area from the d0 taken clock rise of the first data(1), to twr, set wp=low. by setting wp high in the area, write can be cancelled. when it is set wp=high during twr, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. figure 1-(e) wp timing at write cancel scl sda wp hd wp ???? wr d1 d0 a ck a ck data(1) data(n) tsu wp stop condition sd a () sda () thd:sta thd:dat tsu:dat tbuf tpd tdh tlow thigh tr tf scl (input) (output) downloaded from: http:///
datasheet 5/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com block diagram pin configuration pin descriptions function terminal name input / output br24l01a-w br24l02-w br24l04-w br24l08-w br24l16-w br24l32-w br24l64-w a0 input slave address setting not connected slave address setting a1 input slave address setting not connected slave address setting a2 input slave address setting not used slave address setting gnd - reference voltage of all input / output, 0v sda input / output slave and word address, serial data input serial data output scl input serial clock input wp input write protect terminal vcc - connect the power source. 1kbit to 64kbit eeprom arra y control circuit high voltage generating circuit power source voltage detection 7bit 8bit 9bit 10bi t 11bit 12bit 13b it address decoder slave - word address register data register 8bit 7bit 8bit 9bit 10bi t 11bit 12bit 13b it start stop ack *1 *1 1 2 3 4 8 7 6 5 sda scl wp vcc a1 a0 a2 gnd *2 *2 *2 1 7bit : br24l01a-w 8bit : br24l02-w 9bit : br24l04-w 10bit : br24l08-w 11bit : br24l16-w 12bit : br24l32-w 13bit : br24l64-w 2 a0=n.c. : br24l04-w a0, a1=n.c. : br24l08-w a0, a1= n.c. a2=dont use : br24l16-w a0a1 a2 gnd 1 1 1 2 1 3 1 4 1 8 1 6 1 5 br24l01a-w br24l02-w br24l04-w br24l08-w br24l16-w br24l32-w br24l64-w 1 7 vccwp scl sda (top view) downloaded from: http:///
datasheet 6/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 4. "l" output voltage1 vol1-iol1 (vcc=2.5v) figure 5. "l" output voltage vol2-iol2 (vcc=1.8v) figure 2. "h" input voltage vih1,2 figure 3. "l" input voltage vil1,2 (scl, sda, wp) typical performance curves (the following values are typ. ones.) downloaded from: http:///
datasheet 7/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 6. input leak current ili (scl, wp) figure 7. output leak current ilo (sda) figure 9. current consumption at write action icc1 (fscl=400khz) figure 8. current consumpt ion at write action icc1 (fscl=400khz) typical performance curves \ continued icc1 [ ma ] downloaded from: http:///
datasheet 8/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 10. current consumption at read action icc2 (fscl=400khz) figure 12. current consumpt ion at write action icc1 (fscl=100khz) figure 13. current consum ption at read action icc2 (fscl=100khz) figure 11. current consumpt ion at write action icc1 (fscl=100khz) typical performance curves \ continued 1pin mark lot number 1pin mark lot number downloaded from: http:///
datasheet 9/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 14. standby current isb figure 15. scl frequency fscl figure 16. data cl ock h time thigh figure 17. data clock l time tlow typical performance curves \ continued downloaded from: http:///
datasheet 10/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 18. start condition hold time thd:sta figure 19. start condition setup time thd:sta figure 20. input data hold time thd :dat(high) figure 21. input data hold time thd :dat(low) typical performance curves \ continued downloaded from: http:///
datasheet 11/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 22. input data setup time tsu:dat(high) figure 23. input data setup time tsu:dat(low) figure 24. output data delay time tpd0 figure 25. output data delay time tpd1 typical performance curves \ continued downloaded from: http:///
datasheet 12/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 28. noise removal valid time tl (sc l h) figure 29. noise removal valid time tl (sc l l) figure 26. bus release time before transfer start tbuf figure 27. internal write cycle time twr typical performance curves \ continued downloaded from: http:///
datasheet 13/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 30. noise removal valid time tl (sda h) figure 31. noise removal valid time tl (sda l) figure 32. wp setup time tsu:wp figure 33. wp valid time thigh:wp typical performance curves \ continued downloaded from: http:///
datasheet 14/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and ends by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices connected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are master that generates clock and control communicati on start and end, and slave that is controlled by address peculiar to devices. eeprom becomes slave. and the device th at outputs data to bus during data communication is called transmitter, and the dev ice that receives data is called receiver. figure 34. data transfer timing start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start conditi on (start bit) or not, therefore, unless this confdition is satisfied, any command is executed. stop condition (stop bit recongnition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to sh ow whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write comm and, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address in put of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low ' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write action outputs acknowledge signal (ack signal) 'low', at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detects acknowledge signal (ack signal) 'low'. ? when acknowledge signal (ack signal) is detected, a nd stop condition is not s ent from the master ( -com) side, this ic continues data output. when acknowledge signal (ack si gnal) is not detected, this ic stops data transfer, and recognizes stop cindition (stop bit), and ends read action. and this ic gets in status. ii ii a a aa aa a a a - a - - downloaded from: http:///
datasheet 15/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? next slave addresses (a2 a1 a0 --- device address) are fo r selecting devices, and plural ones can be used on a same bus according to the number of device addresses. ? the most insignificant bit (r/w --- read / write) of slave address is used for designating write or read action, and is as shown below. setting r / w to 0 ------- write (setting 0 to word address setting of random read) setting r / w to 1 ------- read ps, p0 to p2 are page select bits. note) up to 4 units br24l04-w, up to 2 units of br24l08-w, and one unit of br24l16-w can be connected. device address is set by 'h' and 'l' of each pin of a0, a1, and a2. type slave address maximum number of connected buses br24l01a-w 1 0 1 0 a2 a1 a0 r/w D 8 br24l02-w 1 0 1 0 a2 a1 a0 r/w D 8 br24l04-w 1 0 1 0 a2 a1 ps r/w D 4 br24l08-w 1 0 1 0 a2 p1 p0 r/w D 2 br24l16-w 1 0 1 0 p2 p1 p0 r/w D 1 br24l32-w 1 0 1 0 a2 a1 a0 r/w D 8 br24l64-w 1 0 1 0 a2 a1 a0 r/w D 8 downloaded from: http:///
datasheet 16/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com write command write cycle ? arbitrary data is written to eeprom. when to write only 1 by te, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. the maximum nu mber of write bytes is specified per device of each capacity. up to 32 arbitrary bytes can be written. (in the case of br24l32 / l64-w) figure 35. byte write cycle (br24l01a/02/04/08/16-w) figure 36. byte write cycle (br24l32/64-w) figure 37. page write cycle (br24l01a/02/04/08/16-w) figure 38. page write cycle (br24l32/64-w) ? data is written to the address designated by word address (n-th address) ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk : up to 8 bytes ( br24l01a-w, br24l02-w) : up to 16bytes (br24l04-w, br24l08-w,br24l16-w) : up to 32bytes (br24l32-w, br24l64-w) and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to "internal address increment" in page 17.) ? as for page write cycle of br24l01a-w and br24l02-w, after the significant 5 bits (4 significant bits in br24l01-w) of word address are designated arbitrarily, and as for p age write command of br24l04-w, br24l08-w, and br24l16-w, after page select bit (ps) of slave address is designated arbi trarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in br24l01a-w, and br24l02-w) is incremented internally, and data up to 16 bytes (up to 8 bytes in br24l01a-w and br24l02-w) can be written. ? as for page write cycle of br24l32-w and br24l64-w, after the significant 7 bits (in the case of br24l32-w) of word address, or the significant 8 bits (in the case of br24l64-w) of word address are designated arbitrarily, by cont inuing data input of 2 byte or more, the address of insignificant 5 bits is incremented i nternally, and data up to 32 bytes can be written. note) figure 39. difference of slave address of each type w r i t e s t a r t r / w a c k s t o p word address(n) dat a (n) sda line a c k a c k data(n+15) a c k slave address 1 0 0 1a 0 a1 a2 wa 7 d0 d7 d0 wa 0 note) *1 *2 a1 a2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w s t o p word address data slave address a0 wa 0 d0 a c k sda line a c k a c k note) *1 *1 as for wa7, br24l01a-w becomes dont care. a1 a2 1 1 0 0 w r i t e s t a r t r / w s t o p 1st word address data slave address a0 d0 a c k sda line a c k a c k note) wa 12 wa 11 * wa 0 a c k 2nd word address d7 *1 * * *1 as for wa12, br24l32-w becomes dont care. *1 as for wa7, br24l01a-w becomes dont care. *2 as for br24l01a/02-w becomes (n+7). *1 as for wa12, br24l32-w becomes dont care. w r i t e s t a r t r / w a c k s t o p 1st w ord address(n) sda line a c k a c k data(n+31) a c k slave address 1 0 0 1a 0 a1 a2 d0 note) *1 data(n) d0 d7 a c k 2nd w ord address(n) wa 0 wa 12 wa 11 * * * 1 0 0 1a 0 a1 a2 *1 *2 *3 *1 in br24l16-w, a2 becomes p2. *2 in br24l08-w, br24l16-w, a1 becomes p1. *3 in br24l04-w, a0 becomes ps, and in br24l08-w and br24l16-w, a0 becomes p0. downloaded from: http:///
datasheet 17/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com notes on write cycle continuous input *1 br24l01a-w becomes dont care. *2 br24l04-w, br24l08-w, and br24l16-w become (n+15). *3 br24l32-w and br24l64-w become (n+31). figure 40. page write cycle note) *1 in br24l16-w, a2 becomes p2. *2 in br24l08-w, br24l16-w, a1 becomes p1. *3 in br24l04-w, a0 becomes ps, and in br24l08-w and in br24l16-w, a0 becomes p0. figure 41. difference of each type of slave address notes on page write cycle list of numbers of page write number of pages 8byte 16byte 32byte product number br24l01a-w br24l02-w br24l04-w br24l08-w br24l16-w br24l32-w br24l64-w the above numbers are maximum bytes for respective types. any bytes below these can be written. in the case br24l02-w, 1 page=8bytes, but the page write cy cle write time is 5ms at maximum for 8byte bulk write. it does not stand 5ms at maximum 8byte=40ms(max.). i a a a aa a i a aa a a a a a a a a note) a next command twr(maximum : 5ms) command is not accepted for this period. at stop (stop bit), write starts. a 1 0 0 1a 0 a1 a2 *1 *2 *3 downloaded from: http:///
datasheet 18/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com internal address increment page write mode (in the case of br24l02-w) for example, when it is started from address 06h,therefore, increment is made as below, 06h 07h 00h 01h ---, which please note. 06h ??? 06 in hexadecimal, therefore, 00 000110 becomes a binary number. write protect (wp) terminal ? write protect (wp) function when wp terminal is set vcc (h level), data rewrite of all ad dresses is prohibited. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this terminal to vcc or gnd, or control it to h level or l level. do not use it open. at extremely low voltage at power on / off, by setti ng the wp terminal 'h', mistake write can be prevented. during twr, set the wp terminal al ways to 'l'. if it is set 'h ', write is forcibly terminated. wa7 ----- wa4 wa3 wa2 wa1 wa0 0 ----- 0 0 0 0 0 0 ----- 0 0 0 0 1 0 ----- 0 0 0 1 0 0 ----- 0 0 1 1 0 0 ----- 0 0 1 1 1 0 ----- 0 0 0 0 0 --------- --------- --------- 06h significant bit is fixed. no digit up increment downloaded from: http:///
datasheet 19/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. in both the read cycles , sequential read cycle is available, and the next address data can be read in succession. figure 42. random read cycle (br24l01a/02/04/08/16-w) figure 43. random read cycle (br24l32/64 -w) figure 44. current read cycle figure 45. sequential read cycle (in the case of current read cycle) ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, and stop condition is not sent from master ( -com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ack signal after d0 and sda signal is started a t scl signal 'h' . ? when 'h' is not input to ack signal after d0, seque ntial read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycle, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition where 'h' is input to ack signal after arbitrary d0 and sda is started at scl signal 'h'. note) figure 46. difference of slave address of each type w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data(n) a c k slave address 10 0 1 a0 a1 a2 wa 7 a0 d0 slave address 10 0 1a1 a2 s t a r t d7 r / w r ea d wa 0 n ote ) *1 it is necessary to input 'h' to the last ack. i a a a a i a a aa a a a a a a a a a a a a a a a a * a a *1 as for wa12, br24l32-w become dont care. *1 as for wa7, br24l01a-w become dont care. s t a r t s t o p sda line a c k data(n) a c k slave address 10 0 1 a0 a1 a2 d0 d7 r / w r e a d note) it is necessary to input 'h' to the last ack. a a a aa a i a a aax a a a a a a note *1 in br24l16-w, a2 becomes p2. *2 in br24l08-w, br24l16-w, a1 becomes p1. *3 in br24l04-w, a0 becomes ps, and in br24l08-w and br24l16-w, a0 becomes p0. 1 0 0 1a 0 a1 a2 *1 *2 *3 downloaded from: http:///
datasheet 20/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com software reset software reset is executed when to avoid malfunction afte r power on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the fi gure below. (refer to figure 47(a), figure 47(b), and figure47(c).) in dummy clock input area, release the sda bus ('h' by pull up). in dummy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefore, if 'h' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. figure 47-(a) the case of dummy clock +start+start+ command input figure 47-(b) the case of start +9 dummy clocks +start+ command input * start command from start input. figure 47-(c) start9+ command input acknowledge polling during internal write execution, all input commands are ignor ed, therefore ack is not sent back. during internal automatic write execution after write cycle input, next command (slave addre ss) is sent, and if the first ack signal sends back 'l', then it means end of write action, while if it sends back 'h', it means now in writing. by use of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, r/w = 0, when to carry out current read cycle after write, slave address r/w = 1 is sent, and if ack signal sends back 'l', then execute word address input and data output and so forth. figure 48. case to continuously write by acknowledge polling 1 2 13 14 scl dummy clock14 start2 2 1 8 9 dummy clock9 start start normal command normal command normal command normal command start9 sda 1 2 3 8 9 7 normal command normal command scl sda scl sda slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack=low is sent back, so input next word address and data in succession. t wr t wr second write command st a r t st a r t s t a r t st a r t s t o p st o p a c k h a c k h a c k l a c k l downloaded from: http:///
datasheet 21/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to cancel write cycle and so forth, pa y attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don't care. set the setup time to rise of d0 taken scl 100ns or more. the area from the rise of scl to take in d0 to the end of intern al automatic write (twr) is cancel valid area. and, when it is set wp='h' during twr, write is ended forcibly, data of address under access is not guaran teed, therefore, writ e it once again. (refer to figure 49.) after execution of forced end by wp, standby status gets in, so there is no need to wait for twr (5ms at maximum). figure 49. wp valid timing command cancel by start condition and stop condition during command input, by continuously inputting start condition and stop condition, command can be cancelled. (refer to figure 50.) however, in ack output area and during data read, sda bus ma y output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read cycle, sequential read cycl e, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out curre nt read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. figure 50. case of cancel by start, stop condition during slave address input ? rise of d0 taken clock scl d0 ack enlarged view scl sda enlarged view ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area write forced end data is not written. data not guaranteed d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address slave address scl sda 1 1 0 0 start condition stop condition downloaded from: http:///
datasheet 22/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the consumption current at action. maximum value of r pu the maximum value of r pu is determined by the following factors. (1)sda rise time to be determined by the capacitance (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda bus and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin 0.2vcc. v cc - i l r pu - 0.2vcc v ih ex. ) when v cc =3v, i l =10 a, v ih =0.7 v cc , from (2) 300 [k ? ] minimum value of r pu the minimum value of r pu is determined by the following factors. (1)when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. (2)v olmax =0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1vcc. v olmax v il -0.1 v cc ex. ) when v cc =3v, v ol =0.4v, i ol =3ma, microcontroller, eeprom v il =0.3v cc from (1) therefore, the condition (2) is satisfied. pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the case there is timing where scl becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k ? to several ten k ? is recommended in consideration of drive performance of output port of microcontroller. a0, a1, a2, wp process process of device address terminals (a0,a1,a2) check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. connect this terminal to pull up or pull down, or vcc or gnd. and, pins (n, c, pin) not used as device address may be set to any of 'h' , 'l', and 'hi-z'. types with n.c.pin br24l16/f/fj/fv/fvt/fvm/fvj-w a0, a1, a2 br24l08/f/fj/fv/fvt/fvm/fvj/nux-w a0, a1 br24l04/f/fj/fv/fvt/fvm/fvj/nux-w a0 process of wp terminal wp terminal is the terminal that prohibits and permits write in hardware manner. in 'h' status, only read is available and write of all address is prohibited. in t he case of 'l', both are available. in the case of use it as an rom, it is recommended to connect it to pull up or vcc. in the case to use both read and write, control wp terminal or connect it to pull down or gnd. r pu 0.8vcc - v ih i l r pu 3-0.4 310 -3 867 [ ? ] and v ol = 0.4 [v] v il = 0.33 = 0.9 [v] figure 51. i/o circuit r pu a br24lxx sda terminal il il microcontroller bus line capacity cbus r pu 0.8 3 - 0.7 3 10 10 -6 v cc - v ol i ol v cc - v ol r pu i ol r pu downloaded from: http:///
datasheet 23/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs bet ween the pull up resistance rpu and the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sda terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. (1)sda rise time to be determined by the capacity (cbu s) of bus line of rpu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. (2)the bus electric potential a to be determined by rpu a nd rs the moment when eeprom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1vcc. minimum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. (v cc v ol )r s r pu +r s + v ol +0.1v cc v il v il v ol 0.1v cc r s 1.1v cc v il r pu example) when v cc =3v, vil=0.3v cc , v ol =0.4v, r pu =20k ? 0.33 0.4 0.13 from(2), r s 1.13 0.33 2010 3 1.67 k ? v cc r s i v cc r s i example)when v cc =3v, i=10ma 3 r s 1010 -3 300 ? microcontroller eeprom 'l' output r s r pu 'h' output over current fi g ure 54. i/o circuit r pu microcontroller r s eeprom figure 52. i/o circuit diagram figure 53. input / output collision timing ack 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda r pu microcontroller r s eeprom i ol a bus line capacity cbus v ol v cc v il figure 55. i/o circuit diagram downloaded from: http:///
datasheet 24/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com i 2 c bus input / output circuit input (a0,a2,scl) input / output (sda) input (a1, wp) notes on power on at power on, in ic internal circuit and se t, vcc rises through unstable low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent this, functions of por circuit and lvcc circuit are equipped. to assure the action, observe the following conditions at power on. 1. set sda = 'h' and scl ='l' or 'h' 2. start power source so as to satisfy the recommended conditions of t r , t off , and vbot for operating por circuit. recommended conditions of t r , t off ,v bot t r t off v bot 10ms or below 10ms or longer 0.3v or below 100ms or below 10ms or longer 0.2v or below figure 56. input pin circuit diagram figure 57. input / output pin circuit diagram figure 58. input pin circuit diagram t off t r vbot 0 v cc figure 59. rise waveform diagram downloaded from: http:///
datasheet 25/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(page 20). c) in the case when the above cond itions 1 and 2 cannot be observed. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and preven ts wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. vcc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfunc tion may occur, therefore, fo r removing these, it is recommended to attach a by pass capacitor (0.1 f) between ic vcc and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. notes for use (1) described numeric values and data are design repres entative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your de cision with sufficient margin in consideration of static characterist ics and transition characteristics and fluc tuations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed volt age and action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperatur e exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical sa fety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that eac h terminal voltage is lower than that of gnd terminal. (5) terminal design in consideration of permissible loss in actual use cond ition, carry out heat design with sufficient margin. (6) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay sufficient attention to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause malfunction, therefore, ev aluate design sufficiently. status of this document the japanese version of this document is fo rmal specification. a customer may use this translation version only for a reference to help reading the formal version. if there are any differences in translation version of this document formal version takes priority. t low t su:dat t dh a fter vcc becomes stable scl v cc sda a fter vcc becomes stable t su:dat figure 60. when scl= 'h' and sda= 'l' figure 61. when scl='l' and sda='l' downloaded from: http:///
datasheet 26/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com ordering information product code description b r 2 4 l x x x x x - w x x bus type 24 i 2 c operating temperature/ power source voltage -40 to+85 / 1.8v to 5.5v capacity 01=1k 08=8k 64=64k 02=2k 16=16k 04=4k 32=32k package f :sop8 fj :sop-j8 fv : ssop-b8 fvt : tssop-b8 fvj : tssop-b8j fvm : msop8 nux : vson008x2030 double cell packaging and forming specification e2 : embossed tape and reel (sop8, sop-j8, ssop-b8,tssop-b8, tssop-b8j) tr : embossed tape and reel (msop8, vson008x2030) lineup package package capacity type quantity capacity type quantity sop8 sop8 sop-j8 sop-j8 ssop-b8 reel of 2500 ssop-b8 reel of 2500 tssop-b8 reel of 3000 tssop-b8 reel of 3000 tssop-b8j reel of 2500 tssop-b8j reel of 2500 msop8 reel of 3000 msop8 reel of 3000 1k vson008x2030 reel of 4000 8k vson008x2030 reel of 4000 sop8 sop8 sop-j8 sop-j8 ssop-b8 reel of 2500 ssop-b8 reel of 2500 tssop-b8 reel of 3000 tssop-b8 reel of 3000 tssop-b8j reel of 2500 tssop-b8j reel of 2500 msop8 reel of 3000 16k msop8 reel of 3000 2k vson008x2030 reel of 4000 sop8 sop8 sop-j8 sop-j8 ssop-b8 reel of 2500 ssop-b8 reel of 2500 32k tssop-b8 reel of 3000 tssop-b8 reel of 3000 sop8 tssop-b8j reel of 2500 64k sop-j8 reel of 2500 msop8 reel of 3000 4k vson008x2030 reel of 4000 downloaded from: http:///
datasheet 27/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information sop8 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin downloaded from: http:///
datasheet 28/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information - continued sop-j8 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin downloaded from: http:///
datasheet 29/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information - continued ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin (unit : mm) ssop-b8 0.08 m 0.3min 0.65 (0.52) 3.0 0.2 0.15 0.1 (max 3.35 include burr) s s 0.1 1234 5 6 7 8 0.22 6.4 0.3 4.4 0.2 +0.06 0.04 0.1 1.15 0.1 ssop-b8 downloaded from: http:///
datasheet 30/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information - continued tssop-b8 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs e2 () 1pin downloaded from: http:///
datasheet 31/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information - continued tssop-b8j direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () 1pin downloaded from: http:///
datasheet 32/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information - continued msop8 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs tr () 1pin downloaded from: http:///
datasheet 33/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information - continued vson008x2030 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tapequantity direction of feed the direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 4000pcs tr () direction of feed reel 1pin downloaded from: http:///
datasheet 34/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com marking diagrams msop8(top view) part number marking lot number 1pin mark part number marking sop8(top view) lot number 1pin mark sop-j8(top view) part number marking lot number 1pin mark tssop-b8j(top view) part number marking lot number 1pin mark vson008x2030 (top view) part number marking lot number 1pin mark tssop-b8(top view) part number marking lot number 1pin mark ssop-b8(top view) part number marking lot number 1pin mark downloaded from: http:///
datasheet 35/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com marking information capacity product name marking package type l01a sop8 l01a sop-j8 l01a ssop-b8 l01a tssop-b8 l01 tssop-b8j l01 msop8 1k l01a vson008x2030 l02 sop8 l02 sop-j8 l02 ssop-b8 l02 tssop-b8 l02 tssop-b8j l02 msop8 2k l02 vson008x2030 l04 sop8 l04 sop-j8 l04 ssop-b8 l04 tssop-b8 l04 tssop-b8j l04 msop8 4k l04 vson008x2030 l08 sop8 l08 sop-j8 l08 ssop-b8 l08 tssop-b8 l08 tssop-b8j l08 msop8 8k l08 vson008x2030 l16 sop8 l16 sop-j8 l16 ssop-b8 l16 tssop-b8 l16 tssop-b8j 16k l16 msop8 l32 sop8 l32 sop-j8 l32 ssop-b8 32k l32 tssop-b8 l64 sop8 64k l64 sop-j8 downloaded from: http:///
datasheet 36/36 br24lxxx-w series (1k 2k 4k 8k 16k 32k 64k) tsz02201-0r2r0g1000290-1-2 21.aug.2012 rev.001 ?2012 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com revision history date revision changes 21.aug.2012 001 new release downloaded from: http:///
datasheet d a t a s h e e t notice - ge rev.002 ? 2014 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (specific applications), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hms products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohms products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used; if flow soldering met hod is preferred, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
datasheet d a t a s h e e t notice - ge rev.002 ? 2014 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohms internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice C we rev.001 ? 2014 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

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